{"id":53005,"date":"2026-08-05T22:13:22","date_gmt":"2026-08-05T22:13:22","guid":{"rendered":"https:\/\/www.monmouth.edu\/career-development\/job\/asic-design-engineer-3\/"},"modified":"2026-08-05T20:23:07","modified_gmt":"2026-08-06T00:23:07","slug":"asic-design-engineer-3","status":"publish","type":"ch_job","link":"https:\/\/www.monmouth.edu\/career-development\/job\/asic-design-engineer-3\/","title":{"rendered":"ASIC Design Engineer"},"content":{"rendered":"

About Black Sesame Technologies<\/strong><\/p>\n

Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533)<\/strong>, Black Sesame Technologies is a leading AI SoC provider. Our mass-produced AI chips are already deployed in the Automotive and Robotics<\/strong> markets, delivering high-performance, automotive-grade compute solutions at scale. Join us to build the future of intelligent machines from the ground up.<\/p>\n

Job Description: ASIC Design Engineer<\/strong><\/p>\n

In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware constraints<\/strong> that make high-performance AI silicon possible. You will focus on optimizing high-speed data path logic<\/strong> while ensuring the design meets rigorous timing and power requirements.<\/p>\n

Responsibilities<\/strong><\/p>\n

\u2022 RTL Design:<\/strong> Implement high-efficiency logic modules using SystemVerilog\/Verilog<\/strong>,<\/p>\n

focusing on AI-specific ALU and datapath<\/strong> components.<\/p>\n

\u2022 STA & Timing:<\/strong> Analyze and fix timing violations (Setup\/Hold) to ensure the design<\/p>\n

closes at target frequencies.<\/p>\n

\u2022 Low Power & PPA:<\/strong> Apply basic low-power techniques (e.g., Clock Gating) and analyze<\/p>\n

their impact on PPA.<\/p>\n

\u2022 Design Sign-off:<\/strong> Run Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain<\/p>\n

Crossing) checks to ensure robust silicon behavior.<\/p>\n

\u2022 Backend Collaboration:<\/strong> Work closely with the physical design team to understand and<\/p>\n

resolve congestion and timing issues.<\/p>\n

Basic Qualifications<\/strong><\/p>\n

\u2022 BS\/MS in Electrical Engineering or Computer Engineering.<\/strong><\/p>\n

\u2022 Hardware Fundamentals:<\/strong> Deep understanding of CMOS logic, Setup\/Hold time,<\/p>\n

Skew\/Jitter, and the impact of PVT (Process, Voltage, Temperature) corners.<\/p>\n

\u2022 STA Knowledge:<\/strong> Familiar with the concept of Static Timing Analysis<\/strong>, including path<\/p>\n

delays, false paths, and multi-cycle paths.<\/p>\n

\u2022 HDL Proficiency:<\/strong> Strong coding skills in SystemVerilog\/Verilog<\/strong> with an emphasis on<\/p>\n

synthesizeable code and hardware-oriented thinking.<\/p>\n

\u2022 Digital Architecture:<\/strong> Understanding of pipelining, stalling, and bypass logic in high-<\/p>\n

performance datapaths.<\/p>\n

\u2022 Scripting:<\/strong> Proficiency in Python, Shell, or TCL<\/strong> (essential for EDA tool interaction).<\/p>\n

You would be a “Star Candidate” if you have:<\/strong><\/p>\n

\u2022 ASIC Flow Experience:<\/strong> Familiarity with the industry-standard ASIC design flow (from<\/p>\n

RTL to GDSII).\u2022 ALU\/Math Foundations:<\/strong> Knowledge of computer arithmetic (Fixed-point, IEEE-754)<\/p>\n

and its hardware implementation.<\/p>\n

\u2022 Advanced CDC:<\/strong> Experience handling complex asynchronous interfaces and<\/p>\n

synchronization techniques.<\/p>\n

\u2022 RISC-V Exposure:<\/strong> Understanding of RISC-V ISA and its pipeline stages.<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"_ch_employer_id":"14029","_ch_external_id":"11278177","_ch_location_state":"","_ch_location_city":"","_ch_is_ocr_job":"","_ch_expiration_date":"2026-09-05","_ch_apply_link":"https:\/\/monmouth.joinhandshake.com\/jobs\/11278177\/share_preview"},"ch_stakeholder":[],"ch_class_year":[],"ch_job_category":[86],"ch_career_skill":[],"ch_industry":[65],"class_list":["post-53005","ch_job","type-ch_job","status-publish","hentry","ch_job_category-full-time","ch_industry-science-technology-innovation"],"_links":{"self":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job\/53005","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job"}],"about":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/types\/ch_job"}],"wp:attachment":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/media?parent=53005"}],"wp:term":[{"taxonomy":"ch_stakeholder","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_stakeholder?post=53005"},{"taxonomy":"ch_class_year","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_class_year?post=53005"},{"taxonomy":"ch_job_category","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job_category?post=53005"},{"taxonomy":"ch_career_skill","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_career_skill?post=53005"},{"taxonomy":"ch_industry","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_industry?post=53005"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}