{"id":20832,"date":"2026-06-24T22:53:39","date_gmt":"2026-06-24T22:53:39","guid":{"rendered":"https:\/\/www.monmouth.edu\/career-development\/job\/asic-design-engineer-2\/"},"modified":"2026-06-25T12:00:47","modified_gmt":"2026-06-25T16:00:47","slug":"asic-design-engineer-2","status":"publish","type":"ch_job","link":"https:\/\/www.monmouth.edu\/career-development\/job\/asic-design-engineer-2\/","title":{"rendered":"ASIC Design Engineer"},"content":{"rendered":"<p><strong>About Black Sesame Technologies<\/strong><\/p>\n<p>Founded in 2016 and <strong>listed on the Hong Kong Stock Exchange (HKEX: 2533)<\/strong>, Black Sesame Technologies is a leading AI SoC provider. Our mass-produced AI chips are already deployed in the <strong>Automotive and Robotics<\/strong> markets, delivering high-performance, automotive-grade compute solutions at scale. As we define our <strong>next-generation AI inference accelerators<\/strong>, we are rapidly <strong>expanding our new Singapore R&amp;D site<\/strong>. Join us to build the future of intelligent machines from the ground up.<\/p>\n<p><strong>Job Description: ASIC Design Engineer<\/strong><\/p>\n<p>In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the <strong>fundamental hardware constraints<\/strong> that make high-performance AI silicon possible. You will focus on optimizing <strong>high-speed datapath logic<\/strong> while ensuring the design meets rigorous timing and power requirements.<\/p>\n<p><strong>Responsibilities<\/strong><\/p>\n<ul>\n<li>\n<strong>RTL Design:<\/strong> Implement high-efficiency logic modules using <strong>SystemVerilog\/Verilog<\/strong>, focusing on AI-specific <strong>ALU and datapath<\/strong> components.<\/li>\n<li>\n<strong>STA &amp; Timing:<\/strong> Analyze and fix timing violations (Setup\/Hold) to ensure the design closes at target frequencies.<\/li>\n<li>\n<strong>Low Power &amp; PPA:<\/strong> Apply basic low-power techniques (e.g., Clock Gating) and analyze their impact on PPA.<\/li>\n<li>\n<strong>Design Sign-off:<\/strong> Run Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure robust silicon behavior.<\/li>\n<li>\n<strong>Backend Collaboration:<\/strong> Work closely with the physical design team to understand and resolve congestion and timing issues.<\/li>\n<\/ul>\n<p><strong>Basic Qualifications<\/strong><\/p>\n<ul>\n<li><strong>BS\/MS in Electrical Engineering or Computer Engineering.<\/strong><\/li>\n<li>\n<strong>Hardware Fundamentals:<\/strong> Deep understanding of CMOS logic, Setup\/Hold time, Skew\/Jitter, and the impact of PVT (Process, Voltage, Temperature) corners.<\/li>\n<li>\n<strong>STA Knowledge:<\/strong> Familiar with the concept of <strong>Static Timing Analysis<\/strong>, including path delays, false paths, and multi-cycle paths.<\/li>\n<li>\n<strong>HDL Proficiency:<\/strong> Strong coding skills in <strong>SystemVerilog\/Verilog<\/strong> with an emphasis on synthesizeable code and hardware-oriented thinking.<\/li>\n<li>\n<strong>Digital Architecture:<\/strong> Understanding of pipelining, stalling, and bypass logic in high-performance datapaths.<\/li>\n<li>\n<strong>Scripting:<\/strong> Proficiency in <strong>Python, Shell, or TCL<\/strong> (essential for EDA tool interaction).<\/li>\n<\/ul>\n<p><strong>You would be a &#8220;Star Candidate&#8221; if you have:<\/strong><\/p>\n<ul>\n<li>\n<strong>ASIC Flow Experience:<\/strong> Familiarity with the industry-standard ASIC design flow (from RTL to GDSII).<\/li>\n<li>\n<strong>ALU\/Math Foundations:<\/strong> Knowledge of computer arithmetic (Fixed-point, IEEE-754) and its hardware implementation.<\/li>\n<li>\n<strong>Advanced CDC:<\/strong> Experience handling complex asynchronous interfaces and synchronization techniques.<\/li>\n<li>\n<strong>RISC-V Exposure:<\/strong> Understanding of RISC-V ISA and its pipeline stages.\u00a0<\/li>\n<\/ul>\n<p>\u00a0<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"_ch_employer_id":"14029","_ch_external_id":"11157644","_ch_location_state":"","_ch_location_city":"","_ch_is_ocr_job":"","_ch_expiration_date":"2026-07-25","_ch_apply_link":"https:\/\/monmouth.joinhandshake.com\/jobs\/11157644\/share_preview"},"ch_stakeholder":[],"ch_class_year":[],"ch_job_category":[86],"ch_career_skill":[],"ch_industry":[65],"class_list":["post-20832","ch_job","type-ch_job","status-publish","hentry","ch_job_category-full-time","ch_industry-science-technology-innovation"],"_links":{"self":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job\/20832","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job"}],"about":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/types\/ch_job"}],"wp:attachment":[{"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/media?parent=20832"}],"wp:term":[{"taxonomy":"ch_stakeholder","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_stakeholder?post=20832"},{"taxonomy":"ch_class_year","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_class_year?post=20832"},{"taxonomy":"ch_job_category","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_job_category?post=20832"},{"taxonomy":"ch_career_skill","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_career_skill?post=20832"},{"taxonomy":"ch_industry","embeddable":true,"href":"https:\/\/www.monmouth.edu\/career-development\/wp-json\/wp\/v2\/ch_industry?post=20832"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}